A single event upset (SEU) generally refers to a change of state of a memory cell, e.g., a change from zero to one or a change from one to zero. In some cases, this transition is induced by an energetic particle such as a cosmic ray, a proton, or the like, striking a device. SEUs can manifest themselves within digital, analog, and optical components of a system or may have effects in surrounding interface circuitry. SEUs are generally referred to as “soft” errors in that a reset or rewriting of the device typically causes normal device behavior after the occurrence of the SEU. In general, any “soft” malfunction of a bit that causes infrequent errors relative to the rate at which such errors are fixed by mitigation techniques and which has a relatively low correlation between errors can be considered an SEU.
In practical terms, for example, an SEU may cause the state of a switch, e.g., a memory or other charge holding circuit structure, to switch from a zero to a one or from a one to a zero. Such a change in state typically causes an error or system fault. Reloading of the system places the changed switch back into the proper state, such that after reloading or reset, the circuit functions as intended, e.g., error free.
PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Other types of PLDs include Complex Programmable Logic Devices (CPLDs), Programmable Logic Arrays (PLAs), and Programmable Array Logic (PAL) devices. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD can include a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
For each type of PLD noted above, the functionality of the device is controlled by data bits provided to the device for that purpose. In consequence, the occurrence of an SEU can be particularly troublesome. For example, an unexpected state change within a configuration memory cell may effectively reconfigure an element of the device, e.g., change operation of an AND gate or change the signal flow by altering the programming of a PIP, thereby causing the IC to implement a different function or cause the circuit to fail. Apart from any effects of the malfunction itself, the PLD must be reloaded or reprogrammed to clear the error.
Designing circuits to overcome SEUs traditionally has been the province of the aerospace industry where imperviousness to cosmic rays has been of greater importance than in consumer-oriented applications. Advances in integrated circuit fabrication techniques, e.g., 90, 65, and 45 nanometer processes, have made even consumer-oriented circuits more susceptible to SEUs.
Mitigation refers to the process of designing a circuit to reduce the vulnerability of the circuit to SEUs. One example of a mitigation technique is triplication, where each module of a circuit design is implemented in triplicate. A voting mechanism is employed in the circuit where the majority state or result is passed along as the output. Due to constraints relating to circuit size, power consumption, timing, and the like, triplication or application of another mitigation technique to the entire circuit design is not always feasible. In the case of a PLD, for example, triplicating each portion of a circuit design may result in a design that is too large to fit within one device. This can add cost, increase power consumption, and increase complexity as more than one PLD would be needed to implement the mitigated circuit design.